LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

-- Dummy_RCV
-- 
-- Inputs:
-- clk = The clock.
-- reset = The reset signal.
-- FWD_to_RCV_LENGTH_ACK = Requests the RCV to send us the length in the next cycle
-- FWD_to_RCV_FRAME_ACK	= Requests the RCV to send us a byte of the data
--
-- Outputs:
-- RCV_to_FWD_DATA = A byte of the actual data
-- RCV_to_FWD_LENGTH = The Rightmost bit is a valid bit, the others are the frame length
-- RCV_to_FWD_FRAMEAVAILABLE = Whether or not RCV currently has an entire frame ready
--

ENTITY DataBuffer IS
   PORT(
	   clk, reset			  : IN STD_LOGIC;
	   IN_DATA	 			  : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	   OUT_ENDINDEX			  : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
	   OUT_DATA				  : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
       );
END DataBuffer;

ARCHITECTURE databuffer_arch OF DataBuffer IS

--COMPONENT One_Bit_Register IS
--	PORT
--	(
--		aclr		: IN STD_LOGIC ;
--		clock		: IN STD_LOGIC ;
--		shiftin		: IN STD_LOGIC ;
--		shiftout		: OUT STD_LOGIC 
--	);
--END COMPONENT;
--
--COMPONENT Three_Bit_Counter_Prototype IS
--	PORT
--	(
--		aclr		: IN STD_LOGIC ;
--		clock		: IN STD_LOGIC ;
--		cnt_en		: IN STD_LOGIC ;
--		q		: OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
--	);
--END COMPONENT;

BEGIN

END databuffer_arch;